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RT8243A/b/c ? ds8243a/b/c-06 january 2014 www.richtek.com 1 ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ordering information note : richtek products are : ? rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. high efficiency, main power supply controller for notebook computers general description the RT8243A/b/c is a dual step down, switch mode power supply (smps) controller which generates logic supply voltages for battery powered systems. it includes two pulse width modulation (pwm) controllers adjustable from 2v to 5.5v and also two fixed 5v/3.3v linear regulators. one of the controllers (ldo5) provides automatic switch over to the byp1 input connected to the main smps1 output for maximized efficiency. an optional external charge pump can be monitored through secfb (rt8243b/c). other features include on board power up sequencing, a power good output, internal soft- start, and a soft discharge output that prevents negative voltage during shutdown. a constant on-time pwm control scheme operates without sense resistors and assures fast load transient response while maintaining nearly constant switching frequency. to eliminate noise in audio applications, an ultrasonic mode is included, which maintains the switching frequency above 25khz. moreover, a diode emulation mode maximizes efficiency for light load applications. the smps1/smps2 switching frequency can be adjustable from 200khz/233khz to 400khz/466khz respectively. the RT8243A/b/c is available in a wqfn-20l 3x3 package, and operates over an extended temperature range from ? 40 c to 85 c. features ? ? ? ? ? 5.5v to 25v input voltage range ? ? ? ? ? 2v to 5.5v output voltage range ? ? ? ? ? no current sense resistor needed ? ? ? ? ? 5v/3.3v linear regulators ? ? ? ? ? 4700ppm/ c r ds(on) current sensing ? ? ? ? ? internal current limit soft-start and soft discharge output ? ? ? ? ? built in ovp/uvp/ocp ? ? ? ? ? selectable operation mode with switcher enable control (RT8243A) ? ? ? ? ? secfb input maintains charge pump voltage (rt8243b/c) ? ? ? ? ? power good indicator (rt8243b/c includes secfb) ? ? ? ? ? rohs compliant and halogen free applications ? notebook computers ? system power supplies ? 3- and 4- cell li+ battery-powered device RT8243A/b/c package type qw : wqfn-20l 3x3 (w-type) lead plating system z : eco (ecological element with halogen free and pb free) pin function with a : enm b : secfb c : secfb, ultrasonic mode
RT8243A/b/c 2 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin configurations (top view) rt8243b/c RT8243A wqfn-20l 3x3 byp1 boot1 entrip2 ton fb1 entrip1 ldo3 ldo5 enldo enm pgood boot2 phase2 phase1 ugate1 lgate1 fb2 vin lgate2 ugate2 15 14 13 12 17 18 19 20 1 2 3 4 9 8 7 6 gnd 21 11 5 16 10 ldo3 ldo5 entrip2 ton fb1 entrip1 enldo secfb pgood boot2 phase2 byp1 boot1 phase1 ugate1 lgate1 fb2 vin lgate2 ugate2 15 14 13 12 17 18 19 20 1 2 3 4 9 8 7 6 gnd 21 11 5 16 10 marking information 8a : product code ymdnn : date code RT8243Azqw 7a : product code ymdnn : date code rt8243bzqw 0b : product code ymdnn : date code rt8243czqw 8a ym dnn 7a ym dnn 0b ym dnn
RT8243A/b/c 3 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit figure 1. RT8243A nb main supply typical application circuit c 8 3 . 3 v RT8243A phase1 lgate1 boot1 ugate1 vin 11 16 19 17 18 phase2 lgate2 boot2 ugate2 fb2 v i n 1 0 f 8 9 7 10 5 c 6 r 1 c 2 0 . 1 f 5 . 5 v t o 2 5 v 21 (exposed pad) gnd n3 l 2 c 7 0 . 1 f r 5 n4 r 6 6 . 5 k + n1 l 1 c 4 c 3 5 v 0 . 1 f r 2 n2 r 3 1 5 k + r 4 1 0 k r 7 1 0 k fb1 1 byp1 20 1 0 f c 1 enldo 12 r 8 1 0 0 k r 9 1 0 0 k entrip2 4 entrip1 2 ldo3 15 c 9 4 . 7 f ldo5 14 pgood 6 r 1 0 1 0 0 k c 1 0 5 v a l w a y s o n ton 3 r ton enm 13 c 5 o p t i o n a l chip enable 3 . 3 v a l w a y s o n v o u t 2 v o u t 1 4 . 7 f
RT8243A/b/c 4 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 2. rt8243b/c nb main supply typical application circuit rt8243b/c phase1 lgate1 boot1 ugate1 vin 11 16 19 17 18 phase2 lgate2 boot2 ugate2 fb2 v i n 1 0 f 8 9 7 10 5 c 6 r 1 c 2 0 . 1 f 5 . 5 v t o 2 5 v 21 (exposed pad) gnd n3 l 2 c 7 c 8 3 . 3 v 0 . 1 f r 5 n4 r 6 6 . 5 k + n1 l 1 c 4 c 3 5 v 0 . 1 f r 2 n2 r 3 1 5 k + r 4 1 0 k r 7 1 0 k fb1 1 byp1 20 1 0 f c 1 enldo 12 r 8 1 0 0 k r 9 1 0 0 k entrip2 4 entrip1 2 off on ldo3 15 c 9 4 . 7 f ldo5 14 pgood 6 r 1 0 1 0 0 k c 1 0 5 v a l w a y s o n ton 3 r ton c 1 1 0 . 1 f c 1 2 0 . 1 f secfb 13 r 1 1 2 0 0 k r 1 2 3 9 k v cp c 1 3 0 . 1 f c 1 4 0 . 1 f c 5 o p t i o n a l c 1 5 3 . 3 v a l w a y s o n v o u t 1 v o u t 2 4 . 7 f
RT8243A/b/c 5 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin no. pin name pin function 1 fb1 smps1 feedback input. connect fb1 to a resistive voltage divider from smps1 output to gnd for adjustable output from 2v to 5.5v. 2 entrip1 channel 1 enable and current limit setting input. connect resistor to gnd to set the threshold for channel 1 synchronous r ds(on) sense. the gnd-phase1 current limit threshold is 1/10th the voltage seen at entrip1 over a 0.5v to 3v range. there is an internal 10 ? a current source from ldo5 to entrip1. leave entrip1 floating or drive it above 4.5v to shut down channel 1. 3 ton on-time/frequency adjustment input. connect to gnd with 56k ? to 100k ? . 4 entrip2 channel 2 enable and current limit setting input. connect resistor to gnd to set the threshold for channel 2 synchronous r ds(on) sense. the gnd-phase2 current limit threshold is 1/10th the voltage seen at entrip2 over a 0.5v to 3v range. there is an internal 10 ? a current source from ldo5 to entrip2. leave entrip2 floating or drive it above 4.5v to shut down channel 2. 5 fb2 smps2 feedback input. connect fb2 to a resistive voltage divider from smps2 output to gnd for adjustable output from 2v to 5.5v. 6 pgood power good output for channel 1 and channel 2 (RT8243A). power good output for channel 1, channel 2 and secfb (rt8243b/c). 7 boot2 boost flying capacitor connection for smps2. connect to an external capacitor according to the typical application circuits. 8 ugate2 upper gate driver output for smps2. ugate2 swings between phase2 and boot2. 9 phase2 switch node for smps2. phase2 is the internal lower supply rail for the ugate2 high side gate driver. phase2 is also the current sense input for the smps2. 10 lgate2 lower gate drive output for smsp2. lgate2 swings between gnd and ldo5. 11 vin supply input for ldo5. 12 enldo master enable input. ldo5/ldo3 is enabled if it is within logic high level and disabled if it is less than the logic low level. leave enldo floating to default enable ldo5/ldo3. 13 enm (RT8243A) mode selection with enable input. pull up to ldo5 (ultrasonic mode) or ldo3 (dem) to turn on both switch channels. short to gnd for shutdown. secfb (rt8243b/c) change pump feedback pin. the secfb is used to monitor the optional external charge pump. connect a resistive divider from the change pump output to gnd to detect the output. if secfb drops below its feedback threshold, an ultrasonic pulse occurs to refresh the charge pump driven by lgate1 or lgate2. if secfb drops below its uv threshold, the switcher channels stop working and enter into discharge-mode. pull up to ldo5 or ldo3 to disable secfb uvp function. 14 ldo5 5v linear regulator output. ldo5 is the supply voltage for the low side mosfet driver and also the analog supply voltage for the device. bypass a minimum 4.7 ? f ceramic capacitor to gnd 15 ldo3 3.3v linear regulator output. bypass a minimum 4.7 ? f ceramic capacitor to gnd. functional pin description
RT8243A/b/c 6 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram pin no. pin name pin function 16 lgate1 lower gate driver output for smps1. lgate1 swings between gnd and ldo5. 17 phase1 switch node smps1. phase1 is the internal lower supply rail for the ugate1 high side gate driver. phase1 is also the current sense input for the smps1. 18 ugate1 upper gate driver output for smps1. ugate1 swings between phase1 and boot 1. 19 boot1 boost flying capacitor connection for smps1. connect to an external capacitor according to the typical application circuits. 20 byp1 switch over source voltage input for ldo5. 21 (exposed pad) gnd analog ground and power ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. enm (RT8243A) secfb (rt8243b/c) smps2 pwm buck controller boot2 ugate2 phase2 lgate2 gnd ldo5 fb2 entrip2 pgood smps1 pwm buck controller boot1 ugate1 phase1 lgate1 ldo5 fb1 entrip1 ldo5 ref switch over threshold vin ldo5 on time ton ldo3 ldo3 byp1 power on sequence clear fault latch enldo + - ldo5 10a ldo5 10a
RT8243A/b/c 7 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. recommended operating conditions (note 4) ? supply input voltage, vin ----------------------------------------------------------------------------------------------- 5.5v t o 25v ? junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c ? ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) ? vin, enldo to gnd ------------------------------------------------------------------------------------------------------ ? 0.3v to 30v ? bootx to phasex dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 6v < 20ns ---------------------------------------------------------------------------------------------------------------------- - ? 2.5v to 6.3v ? entripx, fbx, ton, byp1, pgood, ldo5, ldo3, enm/secfb to gnd ------------------------------- ? 0.3v to 6v ? phasex to gnd dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 30v < 20ns ---------------------------------------------------------------------------------------------------------------------- - ? 8v to 38v ? ugatex to phasex dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 6v < 20ns ---------------------------------------------------------------------------------------------------------------------- - ? 5v to 7.5v ? lgatex to gnd dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 6v < 20ns ---------------------------------------------------------------------------------------------------------------------- - ? 2.5v to 7.5v ? power dissipation, p d @ t a = 25 c wqfn-20l 3x3 ------------------------------------------------------------------------------------------------------------ 3.33 w ? package thermal resistance (note 2) wqfn-20l 3x3, ja ------------------------------------------------------------------------------------------------------- 30 c/w wqfn-20l 3x3, jc ------------------------------------------------------------------------------------------------------ 7.5 c/w ? lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c ? junction temperature ----------------------------------------------------------------------------------------------------- 150 c ? storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c ? esd susceptibility (note 3) hbm (human body model) ---------------------------------------------------------------------------------------------- 2kv
RT8243A/b/c 8 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test con ditions min typ max unit input supply rising threshold -- 5.1 5.5 vin power on reset falling threshold 3.5 -- 4.5 v vin shutdown current i vin_shdn v enldo = gnd -- 20 40 vin standby supply current i vin_sby both smps off -- 250 350 ? a quiescent power consumption i q both smpss on, fbx = 2.1v, byp1 = 5v, enm = 3.3v (RT8243A) -- 5 7 mw smps output and fb voltage fbx, ccm operation -- 2 -- fbx regulation voltage v fbx fbx, dem operation 1.98 2.006 2.03 v output voltage adjustable range smps1, smps2 2 -- 5.5 secfb voltage v secfb rt8243b 1.92 2 2.08 v on time v phase1 = 2v -- 256 -- on-time pulse width t ugatex v in = 20v r ton = 56k ? v phase2 = 2v -- 220 -- ns minimum off-time t lgatex v fbx = 1.8v -- -- 400 ns f smps1 smps1 operating frequency 200 -- 400 frequency range f smps2 smps2 operating frequency 233 -- 466 khz ultrasonic mode frequency f asm rt8243c, v phasex = 50mv 25 -- -- khz soft-start soft-start time t ssx zero to 200mv current limit threshold from entripx enable -- 2 -- ms current sense current limit current source i entripx v entripx = 0.9v 9.4 10 10.6 ? a temperature coefficient of i entripx on the basis of 25 ? c -- 4700 -- ppm/ ? c current limit adjustment range v entripx = i entripx x r entripx 0.5 -- 2.7 v current limit threshold v entripx gnd ? phasex, v entripx = 2v 180 200 225 mv zero-current threshold v zc gnd ? phasex, fbx = 2.1v -- 3 -- mv internal regulator and reference v byp1 = 0v, i ldo5 < 100ma 4.9 5 5.1 v byp1 = 0v, i ldo5 < 100ma , 6.5v < v in < 25v 4.75 -- 5.25 ldo5 output voltage v ldo5 v byp1 = 0v, i ldo5 < 50ma, 5.5v < v in < 25v 4.75 -- 5.25 v (v in = 12v, v enldo = 5v, v entripx = 2v, v byp1 = 5v, no load on ldo5, ldo3, t a = 25 c, unless otherwise specified) electrical characteristics
RT8243A/b/c 9 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit ldo5 output current i short5 v byp1 = 0v, v ldo5 = 4.5v 150 225 300 ma 5v switchover threshold v byp1th falling edge, rising edge with fb1 regulation point 4.53 4.66 4.79 v 5v switch r ds(on) r bypsw v byp1 = 5v, i ldo5 = 50ma -- 1.5 3 ? ldo3 output voltage v ldo3 v byp1 = 0v, i ldo3 < 100ma 3.234 3.3 3.366 v v byp1 = 5v, i ldo3 < 100ma 3.2 3.3 3.46 ldo3 output current i short3 v byp1 = 0v, v ldo3 = 2.9v 80 150 260 ma uvlo ldo5 uvlo threshold v uvlo5 rising edge -- 4.35 4.5 v falling edge 3.9 4.05 4.2 ldo3 uvlo threshold v uvlo3 both smps off -- 2.2 -- power good pgood threshold v pgood pgood detect, rising edge with soft-start delay time. hysteresis = 2.5% ? 14 ? 10 ? 6 % pgood propagation delay t pd_pgood falling edge -- 5 -- ? s pgood leakage current i lk_pgood high state, forced to 5.5v -- -- 1 ? a pgood output low voltage v sink_pgood i sink = 4ma -- -- 0.4 v secfb power good threshold v sfb_pgood secfb with respect to 2v (rt8243b/c) 40 50 60 % fault detection over voltage protection trip threshold v ovp ovp detect, fbx rising edge 108 112 116 % over voltage protection propagation delay t dly_ovp rising edge -- 5 -- ? s under voltage protection trip threshold v uvp uvp detect, fbx falling edge. 53 58 63 % v sfb_uvp uvp detect, secfb falling edge. 0.8 -- 1.2 v under voltage protection shutdown blanking time t sshx from entripx or enm enable -- 5 -- ms thermal shutdown thermal shutdown t sd -- 150 -- c thermal shutdown hysteresis ? t sd -- 10 -- c logic input entripx input voltage v entripx clear fault level/smpsx off level 4.5 -- -- v enldo input voltage v enldo rising edge threshold 1.2 1.6 2 v falling edge threshold 0.9 0.95 1 when enldo is floating (default enable) 2.1 -- -- enm input voltage (RT8243A) v enm clear fault level/smpss off level -- -- 0.8 v smpss on, dem operation 2.3 -- 3.6 smpss on, ultrasonic mode operation 4.5 -- --
RT8243A/b/c 10 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit i fbx v fbx = 0v or 5v ? 1 -- 1 i p1 3 enm/secfb = 0v or 5v ? 1 -- 1 input leakage current i en ldo enldo = 0v or 5v ? 1 -- 3 ? a internal boot switch internal boost charging switch on-resistance r bootx ldo5 to bootx, 10ma -- -- 90 ? power mosfet drivers r ugatesr source, v bootx ? v ugatex = 0.1v -- 5 8 ugatex on-resistance r ugatesk sink, v ugatex ? v phasex = 0.1v -- 2 4 ? r lgatesr source, v ldo5 ? v lgatex = 0.1v -- 5 8 lgatex on-resistance r lgatesk sink, v lgatex = 0.1v -- 1.5 3 ? t lgaterx ugatex off to lgatex on -- 30 -- dead time t ugaterx lgatex off to ugatex on -- 40 -- ns
RT8243A/b/c 11 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics v out1 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) v in = 8v, r ton = 100k , v entrip1 = 1.5v v entrip2 = 5v, enldo = 5v dem asm v out1 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) v in = 12v, r ton = 100k , v entrip1 = 1.5v v entrip2 = 5v, enldo = 5v dem asm v out2 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) v in = 8v, r ton = 100k , v entrip1 = 5v, v entrip2 = 1.5v, enldo = 5v dem asm v out1 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) v in = 20v, r ton = 100k , v entrip1 = 1.5v v entrip2 = 5v, enldo = 5v dem asm v out2 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) v in = 12v, r ton = 100k , v entrip1 = 5v, v entrip2 = 1.5v, enldo = 5v dem asm v out2 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) v in = 20v, r ton = 100k , v entrip1 = 5v, v entrip2 = 1.5v, enldo = 5v dem asm
RT8243A/b/c 12 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. v out1 switching frequency vs. load current 0 20 40 60 80 100 120 140 160 180 200 220 240 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 v in = 8v, r ton = 100k , enldo = vin, v entrip1 = 1.5v, v entrip2 = 5v asm dem v out1 switching frequency vs. load current 0 20 40 60 80 100 120 140 160 180 200 220 240 260 0.001 0.01 0.1 1 10 load current (a) switch frequency (khz) 1 v in = 12v, r ton = 100k , enldo = vin, v entrip1 = 1.5v, v entrip2 = 5v asm dem v out1 switching frequency vs. load current 0 20 40 60 80 100 120 140 160 180 200 220 240 260 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 v in = 20v, r ton = 100k , enldo = vin, v entrip1 = 1.5v, v entrip2 = 5v asm dem v out2 switching frequency vs. load current 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 v in = 12v, r ton = 100k , enldo = vin, v entrip1 = 5v, v entrip2 = 1.5v asm dem v out2 switching frequency vs. load current 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 v in = 20v, r ton = 100k , enldo = vin, v entrip1 = 5v, v entrip2 = 1.5v asm dem v out2 switching frequency vs. load current 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 v in = 8v, r ton = 100k , enldo = vin, v entrip1 = 5v, v entrip2 = 1.5v asm dem
RT8243A/b/c 13 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. v out2 output voltage vs. load current 3.372 3.378 3.384 3.390 3.396 3.402 3.408 3.414 3.420 0.001 0.01 0.1 1 10 load current (a) output voltage (v) v in = 12v, r ton = 100k , enldo = vin, v entrip1 = 5v, v entrip2 = 1.5v asm dem v out1 output voltage vs. load current 5.010 5.013 5.016 5.019 5.022 5.025 5.028 5.031 5.034 0.001 0.01 0.1 1 10 load current (a) output voltage (v) v in = 12v, r ton = 100k , enldo = vin, v entrip1 = 1.5v, v entrip2 = 5v asm dem standby input current vs. input voltage 226 228 230 232 234 236 238 240 6 8 10 12 14 16 18 20 22 24 26 input voltage (v) standby input current ( a) 1 v entrip1 = v entrip2 = 5v, enldo = vin, no load ldo5 output voltage vs. output current 5.048 5.052 5.056 5.060 5.064 5.068 5.072 0 102030405060708090100 output current (ma) output voltage (v) v in = 12v, v entrip1 = v entrip2 = 5v, enldo = vin ldo3 output voltage vs. output current 3.334 3.336 3.338 3.340 3.342 3.344 3.346 3.348 3.350 3.352 3.354 0 102030405060708090100 output current (ma) output voltage (v) v in = 12v, v entrip1 = v entrip2 = 5v, enldo = vin no load battery current vs. input voltage 0.1 1 10 100 6 7 8 9 10111213141516171819202122232425 input voltage (v) battery current (ma ) r ton = 100k , v entrip1 = v entrip2 =1.5v, evldo = vin asm dem
RT8243A/b/c 14 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. power on from enldo time (2ms/div) v in = 12v, v entrip1 = v entrip2 = 1.5v ldo5 (2v/div) ldo3 (2v/div) enldo (10v/div) cp (10v/div) enldo = vin, r ton = 100k , no load shutdown input current vs. input voltage 10 11 12 13 14 15 16 17 18 19 20 21 22 6 8 10 12 14 16 18 20 22 24 26 input voltage (v) shutdown input current ( a) 1 v entrip1 = v entrip2 = 5v, enldo = gnd, no load power off from entrip1 time (4ms/div) rt8243b/c v in = 12v, v entrip1 = v entrip2 = 1.5v, enldo = vin, r ton = 100k , no load v in = 12v, v entrip1 = v entrip2 = 1.5v, enldo = vin, r ton = 100k , no load v out1 (2v/div) pgood (5v/div) entrip1 (5v/div) rt8243b/c power on from entrip1 time (1ms/div) v in = 12v, v entrip1 = v entrip2 = 1.5v, enldo = vin, r ton = 100k , no load v out1 (2v/div) pgood (5v/div) entrip1 (5v/div) rt8243b/c power off from enm time (10ms/div) v out1 (5v/div) pgood (5v/div) enm (5v/div) v out2 (5v/div) RT8243A v in = 12v, v enm = 5v, r ton = 100k , v entrip1 = v entrip2 = 1.5v, enldo = vin, no load power on from enm time (1ms/div) v out1 (2v/div) pgood (5v/div) enm (5v/div) RT8243A v out2 (2v/div) v entrip1 = v entrip2 = 1.5v, enldo = vin, no load v in = 12v, v enm = 5v, r ton = 100k
RT8243A/b/c 15 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ovp time (10ms/div) v in = 12v, r ton = 100k , enldo = vin, no load v out1 (2v/div) pgood (5v/div) v out2 (2v/div) uvp time (100 s/div) v in = 12v, r ton = 100k , enldo = vin v out1 (2v/div) lgate1 (10v/div) ugate1 (50v/div) pgood (5v/div) v out2 dem-mode load transient response time (20 s/div) enldo = vin, i out2 =1a to 8a v out2_ac (50mv/div) inductor current (5a/div) ugate2 (20v/div) lgate2 (5v/div) v in = 12v, r ton = 100k , power off from entrip2 time (20ms/div) v in = 12v, v entrip1 = v entrip2 = 1.5v, enldo = vin, r ton = 100k , no load v out2 (1v/div) pgood (10v/div) entrip2 (5v/div) rt8243b/c v out1 dem-mode load transient response time (20 s/div) v in = 12v, r ton = 100k , enldo = vin, i out1 =1a to 8a v out1_ac (50mv/div) inductor current (5a/div) ugate1 (20v/div) lgate1 (5v/div) power on from entrip2 time (1ms/div) v in = 12v, v entrip1 = v entrip2 = 1.5v, enldo = vin, r ton = 100k , no load v out2 (1v/div) pgood (5v/div) entrip2 (5v/div) rt8243b/c
RT8243A/b/c 16 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information the RT8243A/b/c is a dual, mach response tm drv tm mode synchronous buck controller targeted for notebook system power supply solutions. richtek's mach response tm technology provides fast response to load steps. the topology circumvents the poor load transient timing problems of fixed frequency current mode pwms while avoiding the problems caused by widely varying switching frequency in conventional constant on-time and constant off-time pwm schemes. a special adaptive on- time control trades off the performance and efficiency over wide input voltage range. the RT8243A/b/c includes 5v (ldo5) and 3.3v (ldo3) linear regulators. the ldo5 linear regulator steps down the battery voltage to supply both internal circuitry and gate drivers. the synchronous switch gate drivers are directly powered by ldo5. when v out1 rises above 4.66v, an automatic circuit disconnects the linear regulator and allows the device to be powered by v out1 via the byp1 pin. pwm operation the mach response tm drv tm mode controller relies on the output filter capacitor's effective series resistance (esr) to act as a current sense resistor, so that the output ripple voltage provides the pwm ramp signal. referring to the RT8243A/b/c's function block diagram, the synchronous high side mosfet will be turned on at the beginning of each cycle. after the internal one-shot timer expires, the mosfet will be turned off. the pulse width of this one-shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly constant over the entire input voltage range. another one- shot sets a minimum off-time (400ns typ.). the on-time one-shot will be triggered if the error comparator is high, the low side switch current is below the current limit threshold, and the minimum off-time one-shot has timed out. pwm frequency and on-time control for each specific input voltage range, the mach response tm control architecture runs with pseudo constant frequency by feed forwarding the input and output voltage into the on-time one-shot timer. the high side switch on-time is inversely proportional to the input voltage as measured by v in and proportional to the output voltage. there are two benefits of a constant switching frequency. first, the frequency can be selected to avoid noise sensitive regions such as the 455khz if band. second, the inductor ripple current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. the frequency for 3v smps is set higher than the frequency for 5v smps. this is done to prevent audio frequency ? beating ? between the two sides, which switch asynchronously for each side. the ton pin is connected to gnd through the external resistor, r ton , to set the switching frequency. the RT8243A/b/c adaptively changes the operation frequency according to the input voltage. higher input voltage usually comes from an external adapter, so the RT8243A/b/c operates with higher frequency to have better performance. lower input voltage usually comes from a battery, so the RT8243A/b/c operates with lower switching frequency for lower switching losses. for a specific input voltage range, the switching cycle period is given by : for 5.5v < v in < 6.5v : t s1 = 61.28p x r ton t s2 = 44.43p x r ton for 6.5v < v in < 12v : t s1 = 51.85p x r ton t s2 = 44.43p x r ton for 12v < v in < 25v : t s1 = 45.75p x r ton t s2 = 39.2p x r ton the on-time guaranteed in the electrical characteristics table is influenced by switching delays in the external high side power mosfet. two external factors that influence switching frequency accuracy are resistive drops in the two conduction loops (including inductor and pc board resistance) and the dead time effect. these effects are the largest contributors to the change of frequency with changing load current. the dead time effect increases
RT8243A/b/c 17 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ??? out drop1 on in drop1 drop2 f = (v v ) / (t x (v v v )) where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the resistances in the charging path; and t on is the on-time calculated by the RT8243A/b/c. operation mode selection the RT8243A/b supports two operation modes : diode emulation mode and ultrasonic mode. the rt8243c only supports ultrasonic mode. the operation mode can be set via the enm pin for RT8243A or secfb pin for rt8243b. the effective on-time by reducing the switching frequency as one or both dead times. it occurs only in pwm mode when the inductor current reverses at light or negative load currents. with reversed inductor current, the inductor's emf causes phasex to go high earlier than normal, hence extending the on-time by a period equal to the low to high dead time. for loads above the critical conduction point, the actual switching frequency is : diode emulation mode in diode emulation mode, the RT8243A/b automatically reduces switching frequency at light load conditions to maintain high efficiency. this reduction of frequency is achieved smoothly. as the output current decreases from heavy-load condition, the inductor current is also reduced, and eventually comes to the point that its current valley touches zero, which is the boundary between continuous conduction and discontinuous conduction modes. by emulating the behavior of diodes, the low side mosfet allows only partial negative current to flow when the inductor free wheeling current becomes negative. as the part number RT8243A rt8243b rt8243c pin name enm secfb secfb pin-13 voltage range mode state 4.5v to 5v asm asm asm 2.3v to 3.6v dem dem asm 1.2v to 1.8v asm asm asm below 0.8v shutdown uvp uvp table 1. operation mode setting i l t 0 t on slope = (v in -v out )/l i peak i load = i peak /2 figure 3. boundary condition of ccm/dem in out load(skip) on (v v ) it 2l ? ?? where t on is the on-time. the switching waveforms may appear noisy and asynchronous when light loading causes diode emulation operation. this is normal and results in high efficiency. trade offs in pfm noise vs. light load efficiency is made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load transient response (especially at low input voltage levels). ultrasonic mode the RT8243A/b/c activates a unique type of diode emulation mode with a minimum switching frequency of 25khz, called ultrasonic mode. this mode eliminates audio-frequency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. in ultrasonic mode, the low side switch gate driver signal is ? or ? ed with an internal oscillator (>25khz). once the internal oscillator is triggered, the ultrasonic controller pulls lgatex high and turns on the load current is further decreased, it takes longer and longer time to discharge the output capacitor to the level that requires the next ? on ? cycle. the on-time is kept the same as that in the heavy load condition. in reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous conduction. the transition load point to the light load operation is shown in figure 3. and can be calculated as follows :
RT8243A/b/c 18 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. low side mosfet to induce a negative inductor current. after the output voltage falls below the reference voltage, the controller turns off the low side mosfet (lgatex pulled low) and triggers a constant on-time (ugatex driven high). when the on-time has expired, the controller re- enables the low side mosfet until the controller detects that the inductor current dropped below the zero crossing threshold. linear regulators (ldox) the RT8243A/b/c includes 5v (ldo5) and 3.3v (ldo3) linear regulators. the regulators can supply up to 100ma for external loads. bypass ldox with a minimum 4.7 f ceramic capacitor. when v out1 is higher than the switch over threshold (4.66v), an internal 1.5 p-mosfet switch connects byp1 to the ldo5 pin while simultaneously disconnects the internal linear regulator. current limit setting (entripx) the RT8243A/b/c has cycle-by-cycle current limit control. the current limit circuit employs a unique ? valley ? current sensing algorithm. if the magnitude of the current sense signal at phasex is above the current limit threshold, the pwm is not allowed to initiate a new cycle (figure 4). the actual peak current is greater than the current limit threshold by an amount equal to the inductor ripple current. therefore, the exact current limit characteristic and maximum load capability are a function of the sense resistance, inductor value, and battery and output voltage. i l t i peak i load i limit figure 4. ? valley ? current limit the RT8243A/b/c uses the on resistance of the synchronous rectifier as the current sense element and supports temperature compensated mosfet r ds(on) sensing. the r ilim resistor between the entripx pin and gnd sets the current limit threshold. the resistor, r ilim , is connected to a current source from entripx which is 10 a (typ.) at room temperature. the current source has a 4700ppm/ c temperature slope to compensate the temperature dependency of the r ds(on) . when the voltage drop across the sense resistor or low side mosfet equals 1/10 the voltage across the r ilim resistor, positive current limit will be activated. the high side mosfet will not be turned on until the voltage drop across the mosfet falls below 1/10 the voltage across the r ilim resistor. choose a current limit resistor according to the following equation : v ilim = (r ilim x 10 a) / 10 = i ilim x r ds(on) r ilim = (i ilim x r ds(on) ) x 10 / 10 a carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the current sense signal at phasex and gnd. mount or place the ic close to the low side mosfet. charge pump (secfb) the external 14v charge pump is driven by lgatex. when lgatex is low, c1 will be charged by v out1 through d1. c1 voltage is equal to v out1 minus the diode drop. when lgatex becomes high, c1 transfers the charge to c2 through d2 and charges c2 voltage to v lgatex plus c1 voltage. as lgatex transitions low on the next cycle, c3 is charged to c2 voltage minus a diode drop through d3. finally, c3 charges c4 through d4 when lgatex switches high. thus, the total charge pump voltage, v cp , is : v cp = v out1 + 2 x v lgatex ? 4 x v d where v lgatex is the peak voltage of the lgatex driver which is equal to ldo5 and v d is the forward voltage dropped across the schottky diode. the secfb pin in the rt8243b/c is used to monitor the charge pump via a resistive voltage divider to generate approximately 14v dc voltage and the clock driver uses v out1 as its power supply. in the event where secfb drops below its feedback threshold, an ultrasonic pulse will occur to refresh the charge pump driven by lgatex. if there's an overload on the charge pump in which secfb can not reach more than its feedback threshold, the controller will enter ultrasonic mode. special care should be taken to ensure that enough normal ripple voltage is present on each cycle to prevent charge pump shutdown.
RT8243A/b/c 19 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 5. charge pump circuit connected to secfb mosfet gate driver (ugatex, lgatex) the high side driver is designed to drive high current, low r ds(on) n-mosfet(s). when configured as a floating driver, 5v bias voltage is delivered from the ldo5 supply. the average drive current is also calculated by the gate charge at v gs = 5v times switching frequency. the instantaneous drive current is supplied by the flying capacitor between bootx and phasex pins. a dead time to prevent shoot through is internally generated from high side mosfet off to low side mosfet on and low side mosfet off to high side mosfet on. the low side driver is designed to drive high current low r ds(on) n-mosfet(s). the internal pull down transistor that drives lgatex low is robust, with a 1.5 typical on- resistance. a 5v bias voltage is delivered from the ldo5 supply. the instantaneous drive current is supplied by an input capacitor connected between ldo5 and gnd. for high current applications, some combinations of high and low side mosfets may cause excessive gate drain coupling, which leads to efficiency killing, emi producing, shoot through currents. this is often remedied by adding a resistor in series with bootx, which increases the turn on time of the high side mosfet without degrading the turn-off time. see figure 6. figure 6. increasing the ugatex rise time soft-start the RT8243A/b/c provides an internal soft-start function to prevent large inrush current and output voltage overshoot when the converter starts up. the soft-start (ss) automatically begins once the chip is enabled. during soft- start, the internal current limit circuit gradually ramps up the inductor current from zero. the maximum current limit value is set externally as described in previous section. the soft-start time is determined by the current limit level and output capacitor value. the current limit threshold ramp up time is typically 2ms from zero to 200mv after entripx is enabled. a unique pwm duty limit control that prevents output over voltage during soft-start period is designed specifically for fbx floating. uvlo protection the RT8243A/b/c has ldo5 under voltage lock out protection (uvlo). when the ldo5 voltage is lower than 4.05v (typ.) and the ldo3 voltage is lower than 2.2v (typ.), both switch power supplies are shut off. this is a non- latch protection. power good output (pgood) pgood is an open-drain type output and requires a pull up resistor. pgood is actively held low in soft-start, standby, and shutdown. it is released when both output voltages are above 90% of the nominal regulation point for RT8243A. for rt8243b/c, besides requiring both output voltages to be above 90% of nominal regulation point, the secfb threshold must also be above 50% of nominal regulation point in order for pgood to be released. the pgood signal goes low if either output turns off or is 10% below its nominal regulation point. output over voltage protection (ovp) the output voltage can be continuously monitored for over voltage. if the output voltage exceeds 12% of its set voltage threshold, the over voltage protection is triggered and the lgatex low side gate drivers are forced high. this activates the low side mosfet switch, which rapidly discharges the output capacitor and pulls the input voltage downward. secfb lgate1 vout1 d1 d2 d3 c3 d4 c1 c2 c f r cp1 c4 r cp2 charge pump bootx r boot ugatex v in phasex the robustness of the charge pump can be increased by reducing the charge pump decoupling capacitor and placing a small ceramic capacitor, c f (47pf to 220pf), in parallel with the upper leg of the secfb resistor feedback network, r cp1 , as shown below in figure 5.
RT8243A/b/c 20 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. the RT8243A/b/c is latched once ovp is triggered and can only be released by either toggling enldo, entripx or cycling vin. there is a 5 s delay built into the over voltage protection circuit to prevent false transition. note that latching lgatex high will cause the output voltage to dip slightly negative due to previously stored energy in the lc tank circuit. for loads that cannot tolerate a negative voltage, place a power schottky diode across the output to act as a reverse polarity clamp. if the over voltage condition is caused by a short in high side switch, turning the low side mosfet on 100% will create an electrical short between the battery and gnd, hence blowing the fuse and disconnecting the battery from the output. output under voltage protection (uvp) the output voltage can be continuously monitored for under voltage. if the output is less than 58% of its set voltage threshold, the under voltage protection will be triggered and then both ugatex and lgatex gate drivers will be forced low. the uvp is ignored for at least 5ms (typ.) after a start up or a rising edge on entripx. toggle entripx or cycle vin to reset the uvp fault latch and restart the controller. thermal protection the RT8243A/b/c features thermal shutdown to prevent damage from excessive heat dissipation. thermal shutdown occurs when the die temperature exceeds 150 c. all internal circuitry is inactive during thermal shutdown. the RT8243A/b/c triggers thermal shutdown if ldox is not supplied from v outx , while input voltage on vin and drawing current from ldox are too high. nevertheless, even if ldox is supplied from v outx , overloading ldox can cause large power dissipation on automatic switches, which may still result in thermal shutdown. discharge mode (soft discharge) when entripx is low and a transition to standby or shutdown mode occurs, or the output under voltage fault latch is set, the output discharge mode will be triggered. during discharge mode, an internal switch creates a path for discharging the output capacitors' residual charge to gnd. shutdown mode smps1, smps2, ldo3 and ldo5 all have independent enabling control. drive enldo, entrip1 and entrip2 below the precise input falling edge trip level to place the RT8243A/b/c in its low power shutdown state. the RT8243A/b/c consumes only 20 a of input current while in shutdown. when shutdown mode is activated, the reference turns off. the accurate 0.95v falling edge threshold on enldo can be used to detect a specific analog voltage level and to shutdown the device. once in shutdown, the 1.6v rising edge threshold activates, providing sufficient hysteresis for most applications. power up sequencing and on/off controls (entripx, enm) entrip1 and entrip2 control smps power up sequencing. when the RT8243A/b/c is applied in the single channel mode, entripx disables the respective output when entripx voltage rises above 4.5v. furthermore, when the RT8243A is applied in the dual channel mode, the outputs are enabled when enm voltage rises above 2.3v.
RT8243A/b/c 21 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table1. operation mode truth table mode condition comment power up ldox < uvlo threshold transitions to discharge mode after vin por and after ref becomes valid. ldo5 and ldo3 remain active. run enldo = high, v out1 or v out2 are enabled normal operation. over voltage protection either output >112% of the nominal level. lgatex is forced high. ldo3 and ldo5 are active. exit by vin por or by toggling enldo, entripx, and enm. under voltage protection either output < 58% of the nominal level after 3ms time-out expires and output is enabled both ugatex and lgatex are forced low and enter discharge mode. ldo3 and ldo5 are active. exit by vin por or by toggling enldo, entripx, and enm. discharge either output is still high in standby mode or shutdown mode during discharge mode, there is one path to discharge the output capacitors? residual charge to gnd via an internal switch. standby entripx or enm < startup threshold, enldo = high. ldo3 and ldo5 are active. shutdown enldo = low all circuitry are off. thermal shutdown t j > 150c all circuitry are off. exit by vin por or by toggling enldo, entripx, and enm. table 2. power up sequencing (RT8243A) enldo (v) enm (v) entrip1 (v) entrip2 (v) ldo5 ldo3 smps1 smps2 low low x x off off off off ?>1.6v? => high low x x on on off off ?>1.6v? => high ?>2.3v? => high off off on on off off ?>1.6v? => high ?>2.3v? => high off on on on off on ?>1.6v? => high ?>2.3v? => high on on on on on on ?>1.6v? => high ?>2.3v? => high on off on on on off
RT8243A/b/c 22 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. output voltage setting (fbx) connect a resistive voltage divider at the fbx pin between v outx and gnd to adjust the output voltage between 2v and 5.5v (figure 7). choose r2 to be approximately 10k , and solve for r1 using the equation : ?? ?? ?? ?? ?? ?? ?? out fbx r1 vv x 1 r2 where v fbx is 2v (typ.). ugatex phasex lgatex pgnd fbx gnd r1 r2 voutx v in figure 7. setting v outx with a resistive voltage divider output inductor selection the switching frequency (on-time) and operating point (% ripple or lir) determine the inductor value as shown below : ? ? on in outx load(max) t x (v v ) l lir x i where lir is the ratio of the peak-to-peak ripple current to the average inductor current. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current, i peak : i peak = i load(max) + [ (lir / 2) x i load(max) ] the calculation above shall serve as a general reference. to further improve transient response, the output inductance can be further reduced. of course, besides the inductor, the output capacitor should also be considered when improving transient response. output capacitor selection the capacitor value and esr determine the amount of output voltage ripple and load transient response. thus, the capacitor value must be greater than the largest value calculated from below equations. 2 load on off(min) sag out in on outx on off(min) (i ) l (t t ) v 2 x c v t v (t + t ) ???? ? ?? ??? ?? () 2 load soar out outx il v 2c v ?? ? ?? p p load(max) out 1 v lir x i esr + 8 x c f ? ?? ?? ?? ? ?? where v sag and v soar are the allowable amount of undershoot and overshoot voltage during load transient, v p-p is the output ripple voltage, and t off(min) is the minimum off-time. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn-20l 3x3 package, the thermal resistance, ja , is 30 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (30 c/w) = 3.33w for wqfn-20l 3x3 package
RT8243A/b/c 23 ds8243a/b/c-06 january 2014 www.richtek.com ? copyright 2014 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 8 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 8. derating curve of maximum power dissipation layout considerations layout is very important in high frequency switching converter design. improper pcb layout can radiate excessive noise and contribute to the converter?s instability. certain points must be considered before starting a layout with the RT8243A/b/c. ? place the filter capacitor close to the ic, within 12mm (0.5 inch) if possible. ? keep current limit setting network as close as possible to the ic. routing of the network should avoid coupling to high-voltage switching node. ? connections from the drivers to the respective gate of the high side or the low side mosfet should be as short as possible to reduce stray inductance. use 0.65mm (25 mils) or wider trace. ? all sensitive analog traces and components such as fbx, entripx, pgood, and ton should be placed away from high voltage switching nodes such as phasex, lgatex, ugatex, or bootx nodes to avoid coupling. use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. ? place ground terminal of vin capacitor(s), v outx capacitor(s), and source of low side mosfets as close to each other as possible. the pcb trace of phasex node, which connects to source of high side mosfet, drain of low side mosfet and high voltage side of the inductor, should be as short and wide as possible. 0.0 0.6 1.2 1.8 2.4 3.0 3.6 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT8243A/b/c 24 ds8243a/b/c-06 january 2014 www.richtek.com richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 2.900 3.100 0.114 0.122 d2 1.650 1.750 0.065 0.069 e 2.900 3.100 0.114 0.122 e2 1.650 1.750 0.065 0.069 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 20l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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